In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, data are placed on a data bus by the memory device in synchronism with the external clock signal, and the memory device must provide the data at the proper times for the data to be valid. To provide the data at the correct times, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to thereby clock the data onto the data bus. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully output the data at the proper times. In the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. To increase the rate at which data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency is in excess of 100 MHZ. As the frequency of the external clock signal increases, however, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result, the data applied to the data bus may not be valid at the proper times to be latched.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another. FIG. 1 is a functional block diagram illustrating a conventional delay-locked loop 100 including a variable delay line 102 that receives a clock buffer signal CLKBUF and generates a delayed clock signal CLKDEL in response to the clock buffer signal. The variable delay line 102 controls a variable delay VD of the CLKDEL signal relative to the CLKBUF signal in response to a delay adjustment signal DADJ. A feedback delay line 104 generates a feedback clock signal CLKFB in response to the CLKDEL signal, the feedback clock signal having a model delay D1+D2 relative to the CLKDEL signal. The D1 component of the model delay D1+D2 corresponds to a delay introduced by an input buffer 106 that generates the CLKBUF signal in response to an external clock signal CLK, while the D2 component of the model delay corresponds to a delay introduced by an output buffer 108 that generates a synchronized clock signal CLKSYNC in response to the CLKDEL signal. Although the input buffer 106 and output buffer 108 are illustrated as single components, each represents all components and the associated delay between the input and output of the delay-locked loop 100. The input buffer 106 thus represents the delay D1 of all components between an input that receives the CLK signal and the input to the variable delay line 102, and the output buffer 108 represents the delay D2 of all components between the output of the variable delay line and an output at which the CLKSYNC signal is developed. For example, the output buffer 108 may represent all of components in a data path in the memory device through which the data propagates to be provided onto the data bus. The CLKSYNC signal can then be used to clock the output data latches such that the data is provided in synchronicity with the CLK signal applied to the memory device.
The delay-locked loop 100 further includes a phase detector 110 that receives the CLKFB and CLKBUF signals and generates a delay control signal DCONT having a value indicating the phase difference between the CLKBUF and CLKFB signals. One implementation of a phase detector is described in U.S. Pat. No. 5,946,244 to Manning (Manning), which is assigned to the assignee of the present patent application and which is incorporated herein by reference. A delay controller 112 generates the DADJ signal in response to the DCONT signal from the phase detector 110, and applies the DADJ signal to the variable delay line 102 to adjust the variable delay VD. The phase detector 110 and delay controller 112 operate in combination to adjust the variable delay VD of the variable delay line 102 as a function of the detected phase between the CLKBUF and CLKFB signals.
In operation, the phase detector 110 detects the phase difference between the CLKBUF and CLKFB signals, and the phase detector and delay controller 112 operate in combination to adjust the variable delay VD of the CLKDEL signal until the phase difference between the CLKBUF and CLKFB signals is approximately zero. More specifically, as the variable delay VD of the CLKDEL signal is adjusted the phase of the CLKFB signal from the feedback delay line 104 is adjusted accordingly until the CLKFB signal has approximately the same phase as the CLKBUF signal. When the delay-locked loop 100 has adjusted the variable delay VD to a value causing the phase shift between the CLKBUF and CLKFB signals to equal approximately zero, the delay-locked loop is said to be “locked.” When the delay-locked loop 100 is locked, the CLK and CLKSYNC signals are synchronized. This is true because when the phase shift between the CLKBUF and CLKFB signals is approximately zero (i.e., the delay-locked loop 100 is locked), the variable delay VD has a value of NTCK−(D1+D2) as indicated in FIG. 1, where N is an integer and TCK is the period of the CLK signal. When VD equals NTCK−(D1+D2), the total delay of the CLK signal through the input buffer 106, variable delay line 102, and output buffer 108 is D1+NTCK−(D1+D2)+D2, which equals NTCK. Thus, the CLKSYNC signal is delayed by NTCK relative to the CLK signal and the two signals are synchronized since the delay is an integer multiple of the period of the CLK signal. Referring back to the discussion of synchronous memory devices above, the CLK signal corresponds to the external clock signal and the CLKSYNC signal corresponds to the internal clock signal.
FIG. 2 is a signal timing diagram illustrating various signals generated during operation of the delay-locked loop 100 of FIG. 1. In response to a rising-edge of the CLK signal at a time T0, the CLKBUF signal goes high the delay D1 later at a time T1. Initially, the variable delay VD as a value VD1, causing the CLKDEL signal to go high at a time T3 and the CLKSYNC signal to go high at a time T4. At this point, note that the positive-edge of the CLKSYNC signal at the time T4 is not synchronized with the CLK signal, which transitions high at a time T5. In response to the rising-edge of the CLKDEL signal at the time T3, the CLKFB goes high at a time T6, which occurs before a positive-edge of the CLKBUF signal occurring at a time T7. Thus, the positive-edge of the CLKFB signal occurs at the time T6 while the positive-edge of the CLKBUF occurs at the time T7, indicating there is a phase shift between the two signals. The phase detector 110 (FIG. 1) detects this phase difference, and generates the DCONT signal just after the time T7 at a time T8 which, in turn, causes the delay controller 112 (FIG. 1) to generate the DADJ signal to adjust the value of the variable delay VD to a new value VD2.
In response to the new variable delay VD2, the next rising-edge of the CLKDEL signal occurs at a time T9. The CLKSYNC signal transitions high the delay D2 later at a time T10 and in synchronism with a rising-edge of the CLK signal. At this point, the delay-locked loop 100 is locked. In response to the positive-edge transition of the CLKDEL signal at the time T9, the CLKFB signal transitions high at a time T11 in synchronism with the CLKBUF signal. Once again, the phase detector 110 (FIG. 1) detects the phase difference between the CLKBUF and CLKFB signals, which in this case is approximately zero, and generates the DCONT signal just after the time T11 in response to the detected phase difference. In this situation, the generated DCONT signal would not cause the variable delay VD2 to be adjusted since the delay-locked loop 100 is locked. Moreover, although the relative phases of the CLKBUF and CLKFB signals is detected in response to each rising-edge of these signals, the variable delay VD may not be adjusted immediately even where such a phase difference is detected. For example, the variable delay VD may be adjusted only when a phase difference between the CLKFB and CLKBUF signals exists for a predetermined time or exceeds a predetermined magnitude. In this way, the phase detector 110 and delay controller 112 can provide a sort of “filtering” of jitter or variations in the CLK signal, as will be understood in the art.
In the delay-locked loop 100, each cycle of the CLK signal the phase detector 110 compares rising-edges of the CLKBUF and CLKFB signals and generates the appropriate DCONT signal to incrementally adjust the variable delay VD until the delay-locked loop 100 is locked. The phase detector 110 could also compare falling-edges of the CLKBUF and CLKFB signals, as in the previously mentioned Manning patent. In this way, the delay-locked loop 100 incrementally adjusts the variable delay VD once each cycle of the CLK signal. Although the example of FIG. 2 illustrates the delay-locked loop 100 as locking and therefore synchronizing the CLK and CLKSYNC signals after only two cycles of the CLK signal, the delay-locked loop typically takes as many as 200 cycles of the CLK signal to lock. Before the delay-locked loop 100 is locked, the CLKSYNC signal cannot be used to clock output latches of the synchronous memory device containing the delay-locked loop. As a result, the time it takes to lock the delay-locked loop 100 may slow the operation of the associated synchronous memory device. For example, in a conventional double data rate (DDR) SDRAM, the delay-locked loop is automatically disabled when the SDRAM enters a self-refresh mode of operation. Upon exiting the self-refresh mode, 200 cycles of the applied CLK signal must then occur before data can be provided by the SDRAM.
In the delay-locked loop 100, the variable delay line 102 typically is formed from a number of serially-connected individual delay stages, with individual delay stages being added or removed to adjust the variable delay VD, as will be understood by those skilled in the art. For example, a plurality of serially-connected inverters could be used to form the variable delay line 102, with the output from different inverters being selected in response to the DADJ to control the variable delay VD. A large number of stages in the variable delay line 102 is desirable with each stage having an incremental delay to provide better resolution in controlling the value of the variable delay VD. In addition, the variable delay line 102 must be able to provide the maximum variable delay VD corresponding to the CLK signal having the lowest frequency in the frequency range over which the delay-locked loop is designed to operate. This is true because the variable delay line 102 must provide a variable delay VD of NTCK−(D1+D2), which will have its largest value when the period of the CLK signal is greatest, which occurs at the lowest frequency of the CLK signal.
As previously explained, the delay-locked loop 100 can only operate over a limited frequency range due to the maximum delay available from the variable delay line 102. In many memory device applications, the minimum frequency that a delay-locked loop can accommodate is one-half the maximum operating frequency of the memory device in which the delay-locked loop is located. For example, a synchronous memory device rated at a maximum clock frequency of 100 MHz typically includes a delay-locked loop having a variable delay line that can accommodate a clock frequency as low as 50 MHz. However, in some instances, it may desirable to be able to operate the device at a frequency less than one-half of the maximum operating frequency, or in the case of the previously mentioned synchronous memory device, at a clock frequency less than 50 MHz.
One such instance is for the purpose of power efficiency. It is generally the case that the higher the clock frequency at which a memory device is operated, the higher the power consumed. However, in some memory device applications, the frequency at which a memory device needs to output data does not necessarily need to be at its maximum operating frequency. Thus, it would be advantageous to be able to operate a memory device at lower clock frequency to take advantage of any power savings that may be available. For the greatest power efficiency, the lowest operating frequency that can be sustained will yield the greatest benefit. For example, in the case of computer graphics applications, a high operating frequency is desirable when data needs to be read from and written to memory quickly, such as when significant computation is necessary in generating pixel information for computer graphics images that are changing rapidly. This is the case for many computer video games where there is motion through a world space defined by three-dimensional geometric information that needs to be translated into a two-dimensional image for display. The ability to access data from memory at a high frequency is critical in creating the impression of smooth motion, and consequently, memory devices should be operating at the maximum clock frequency to facilitate the graphics processing. However, operating the graphics system at a low operating frequency may also be desirable under some circumstances, such as when the images are changing relatively slowly, or only a small portion of the pixels displayed need to be modified each time the image is refreshed. An example of this situation is the case of a screen saver where images remain relatively static until refreshed, or where movement is relatively slow. Under these circumstances, the rate at which data can be accessed from a memory device can be considerably slower, and consequently, operating the memory of the graphics system at a lower frequency than in the situation where high frequency is desirable will yield power savings.
As previously discussed, the rate at which data is provided by the memory device is typically synchronized with the input clock signal, which is generally a fixed frequency clock signal. However, even if the frequency of the input clock signal could be adjusted to a lower frequency, there remains the issue with the limited range of clock frequencies that conventional delay-locked loops can accommodate. As previously discussed, the minimum frequency is often one-half of the maximum operating frequency, which may still be higher than what is desirable under certain conditions. In this situation, to manage power consumption more efficiently, it would be desirable to then operate the memory device at a frequency lower than what is possible with conventional memory devices.
One approach to overcoming the limitation of one-half the maximum operation frequency is to use a delay-locked loop having a variable delay line 102 with a greater range of adjustable delay. Moreover, it is desirable to have a large number of stages in the variable delay line 102 with each stage having an incremental delay to provide better resolution in controlling the value of the variable delay. A consequence of having the desired fine resolution and broad range of variable delay is that it can result in the delay line consisting of a large number of individual delay stages, which will consume a relatively large amount of space on a semiconductor substrate in which the delay-locked loop and other components of the synchronous memory device are formed. Moreover, such a large number of individual delay stages can result in significant power consumption by the delay-locked loop, which may be undesirable particularly in applications where the synchronous memory device is contained in a portable battery-powered device.